Class Objective:
           Training based on Industrial Curriculum & Requirement
           Focus to Every Students
           Practical Coverage to Problems & Layouts
           Preparation for Interviews and Exams
           Project Completion with Satisfaction & Learning

Course Outline:

    Orientation:
           Training based on Industrial Curriculum & Requirement

    Introduction to VLSI Design:
           Evolution
           History
           CMOS Features
           Types of ASICs
           Reconfigurable Logic

    Applicative Digital Design:

    Combinational Designs:

           Universal Gates
           Design of Circuits using only NAND and NOR
           Combinational Design with Live Problems
           Basic ALU Design

    VHDL:
           Introduction
           Features
           Constructs
           Design
           Synthesis of Combinational Circuits
           Implementation

    Applicative Digital Design:
           Excitation tables and waveforms of various Flip-Flops
           VHDL codes and their simulation using models
           Implementation of FPGA
           Synchronous and Asynchronous Counters

    Application of Counters:
           Register-Shift Registers
           VHDL Codes and their simulation using models
           Implementation of FPGA

    Finite State Machine:
           Mealy
           Moore
           Application of FSM

    PLD Architecture:
           CPLD
           FPGA

    Project ( A Complete Digital System Implementing Task):
    Revision :

    Duration: 45 Days.:
    Eligibility: B.E/B.Tech, B.Sc, Diploma, M.Tech & Professionals. :